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US 2014/0351308 A1Published application
System and method for dynamically reducing power consumption of floating-point logic
AssigneeNVIDIA Corporation
InventorsDavid C. Tannenbaum, Srinivasan Iyer
Life of this patent
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Abstract
A system and method are provided for dynamically reducing power consumption of floating-point logic. A disable control signal that is based on a characteristic of a floating-point format input operand is received and a portion of a logic circuit is disabled based on the disable control signal. The logic circuit processes the floating-point format input operand to generate an output.
Claims20
A method, comprising:
- receiving a disable control signal that is based on a characteristic of a floating-point format input operand;
- disabling a portion of a logic circuit based on the disable control signal;
- and
- processing the floating-point format input operand by the logic circuit to generate an output.
1 more element
A processing unit, comprising:
- arithmetic logic circuitry configured to:
- receive a disable control signal that is based on a characteristic of a floating-point format input operand;
- disable a portion of the arithmetic logic circuitry based on the disable control signal;
- and
- process the floating-point format input operand to generate an output.
2 more elements
A system, comprising:
- a memory;
- and
- a processing unit, comprising:
- arithmetic logic circuitry configured to:
- receive a disable control signal that is based on a characteristic of a floating-point format input operand;
- disable a portion of the arithmetic logic circuitry based on the disable control signal;
- and
- process the floating-point format input operand to generate an output.
5 more elements
Dependencies are inferred from the claim text.