Method for forming dual sti structure
AssigneeShanghai Huali Microelectronics Corporation
InventorsYushu YANG, Wei QIN, Haihui HUANG
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Abstract
A method for forming dual shallow trench isolation (STI) structure, which includes a first etching process for forming a deep STI structure in a logic region using a hard mask layer as a mask and a second etching process for forming a shallow STI structure in a pixel region using a photoresist as a mask. Independence between these two etching processes can avoid the prior art problems of double slope profile of the sidewalls of the deep STI structure and a thickness inconsistency of the hard mask layer between on the pixel region and on the logic region.
Claims16
A method for forming dual STI structure, comprising the following steps in the sequence set forth:
- providing a silicon wafer having a first region and a second region;
- forming a hard mask layer on the silicon wafer;
- forming a first opening in the hard mask layer to expose a portion of the silicon wafer in the second region;
- etching the silicon wafer using the hard mask layer as a mask to form a deep STI structure in the second region;
- forming an insulating anti-reflection layer filling the deep STI structure and covering the hard mask layer;
- coating a photoresist layer on the insulating anti-reflection layer, and forming a second opening in the photoresist layer to expose a portion of the insulating anti-reflection layer in the first region;
- and
- sequentially etching the insulating anti-reflection layer, the hard mask layer and the silicon wafer using the photoresist layer as a mask to form a shallow STI structure in the first region.
A method of forming a complementary metal-oxide-semiconductor (CMOS) image sensor, comprising the following steps in the sequence set forth:
- providing a silicon wafer having a pixel region and a logic region;
- forming a hard mask layer on the silicon wafer;
- forming a first opening in the hard mask layer to expose a portion of the silicon wafer in the logic region;
- etching the silicon wafer using the hard mask layer as a mask to form a deep STT structure in the logic region;
- forming an insulating anti-reflection layer filling the deep STI structure and covering the hard mask layer;
- coating a photoresist layer on the insulating anti-reflection layer, and forming a second opening in the photoresist layer to expose a portion of the insulating anti-reflection layer in the pixel region;
- and
- sequentially etching the insulating anti-reflection layer, the hard mask layer and the silicon wafer using the photoresist layer as a mask to form a shallow STI structure in the pixel region.
Dependencies are inferred from the claim text.