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US 2014/0349458 A1Published application
Source and Drain Dislocation Fabrication in FinFETs
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsZhiqiang Wu, Wen-Hsing Hsieh, Hua Feng Chen, Ting-Yun Wu, Carlos H. Diaz, Tzer-Min Shen, Ya-Yun Cheng
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Abstract
A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.
Claims20
A method comprising:
- forming a gate dielectric on sidewalls of a middle portion of a semiconductor fin;
- forming a gate electrode over the gate dielectric;
- forming a source/drain region on a side of the gate electrode;
- forming a strained capping layer, wherein the strained capping layer comprises a portion overlapping the gate electrode;
- after the forming the strained capping layer, performing an annealing to form a dislocation plane in a semiconductor material underlying the strained capping layer;
- and
- after the annealing, removing the strained capping layer.
4 more elements
A method comprising:
- forming a gate dielectric on top surfaces and sidewalls of middle portions of semiconductor fins;
- forming a gate electrode over the gate dielectric;
- recessing end portions of the semiconductor fins to expose first semiconductor regions underlying the semiconductor fin, with the end portions on a same side of the gate electrode;
- etching through a Shallow Trench Isolation (STI) region between the end portions of the semiconductor fins to expose a second semiconductor region overlapped by the STI region;
- and
- epitaxially growing a semiconductor capping layer from the first semiconductor regions and the second semiconductor region;
- forming a strained capping layer on the semiconductor capping layer;
- performing a pre-amorphization implantation on the strained capping layer;
- and
- performing an annealing to form a dislocation plane in the semiconductor capping layer.
7 more elements
A method comprising:
- forming a gate dielectric on sidewalls of a middle portion of a semiconductor fin;
- forming a gate electrode over the gate dielectric;
- forming a source/drain region in an end portion of the semiconductor fin;
- etching a portion of the source/drain region to form a recess, with a remaining portion of the source/drain region left un-etched after the etching;
- epitaxially growing a semiconductor capping layer in the recess;
- forming a strained capping layer on the semiconductor capping layer;
- performing a pre-amorphization implantation to amorphize the strained capping layer and the remaining portion of the source/drain region;
- performing an annealing to form a dislocation plane in the semiconductor capping layer and the remaining portion of the source/drain region;
- and
- after the annealing, removing the strained capping layer.
7 more elements
Dependencies are inferred from the claim text.