Methods of fabricating three-dimensional semiconductor memory devices using direct strapping line connections

A method comprising:

• forming a mold stack comprising alternately arranged sacrificial layers and insulating layers on a substrate;
• forming rows of vertical channel regions passing through the mold stack;
• forming respective trenches in the mold stack between adjacent ones of the rows of the vertical channel regions and exposing portions of the substrate, the trenches each having linear first portions of a first width and spaced-apart widened second portions having a second width greater than the first width;
• forming common source regions in the exposed portions of the substrate;
• forming respective gate stacks between respective adjacent pairs of the trenches from the mold stack;
• forming respective insulation regions in respective ones of the trenches, wherein portions of the insulation regions in the widened second portions of the trenches have holes therethrough that expose portions of the common source regions;
• forming conductive plugs in the holes and connected to the common source regions;
• forming respective strapping lines on respective ones of the insulation regions and in direct electrical contact with the plugs;
• and
• forming a plurality of bit lines crossing the strapping lines and electrically connected to the vertical channel regions.