US 2014/0349447 A1Published application

Method of manufacturing semiconductor device

AssigneeRenesas Electronics Corporation

InventorsHiroshi Fujii, Shigeki Tanaka, Kazuaki Yoshida

Life of this patent

Estimating the term…

Loading patent…

Abstract

To stably remove a resin body formed in a supply route of a resin in a sealing step. A leadframe has, in a sub-runner portion thereof, a sub-through-hole. The sub-through-hole has, along a first direction along which the sub-runner portion extends, a first portion located on the side of a main-runner portion and a second portion located on the side of a gate portion relative to the first portion. In a plan view, an opening width of the sub-through-hole in the first direction is greater than that of the sub-through-hole in a second direction perpendicular to the first direction. In a plan view, an opening width of the sub-through-hole in the second direction gradually decreases from the first portion to an end portion of the second portion on the side of the gate portion.

Claims17

Dependent claims

A method of manufacturing a semiconductor device, comprising the steps of:

(a) providing a leadframe having:
a first surface;
a second surface opposite to the first surface;
a device forming portion having a first region of the first surface and a first region of the second surface;
a frame portion having a second region of the first surface and a second region of the second surface and formed around the device forming portion in plan view;
a main-runner portion formed over the first surface of the frame portion along a first direction;
a gate portion linked with the device forming portion;
a sub-runner portion formed over the first surface of the frame portion so as to link the gate portion with the main-runner portion;
a main-through-hole formed in the main-runner portion so as to extend from one of the first surface and the second surface to the other;
and a sub-through-hole formed in the sub-runner portion so as to extend from one of the first surface and the second surface to the other,
wherein the sub-through-hole has, along a second direction along which the sub-runner portion extends, a first portion located on the side of the main-runner portion and a second portion located on the side of the gate portion relative to the first portion,
wherein in plan view, a maximum opening width of the sub-through-hole in the second direction is greater than a maximum opening width of the sub-through-hole in a third direction perpendicular to the second direction, and
wherein in plan view, an opening width of the sub-through-hole in the third direction gradually decreases from the first portion to an end portion of the second portion on the side of the gate portion,
(b) after the step (a), arranging a semiconductor chip over the device forming portion;
(c) after the step (b), supplying a resin into a cavity of the molding die covering the semiconductor chip at the device forming portion through a main-runner of a molding die covering the main-runner portion, a sub-runner of the molding die covering the sub-runner portion, and the gate portion of the leadframe, thereby forming a device sealing portion that seals the semiconductor chip at the device forming portion, a main-runner sealing portion at the main-runner portion, and a sub-runner sealing portion at the sub-runner portion;
and
(d) after the step (c), inserting a pin into each of the main-through-hole and the sub-through-hole from the second surface side of the leadframe and thereby separating the main-runner sealing portion and the sub-runner sealing portion from the leadframe.

14 more elements

A method of manufacturing a semiconductor device, comprising the following steps of:

(a) providing a leadframe having:
a first surface;
a second surface opposite to the first surface;
a plurality of device forming portions having a first region of the first surface and a first region of the second surface and formed along a first direction;
a frame portion having a second region of the first surface and a second region of the second surface and formed around each of the device forming portions in plan view;
a main-runner portion formed in the first surface of the frame portion along the first direction;
a first gate portion linked with a first device forming portion of the device forming portions;
a first sub-runner portion formed in the first surface of the frame portion so as to link the first gate portion with the main-runner portion;
a main-through-hole formed in the main-runner portion so as to extend from one of the first surface and the second surface to the other one;
a first sub-through-hole formed in the first sub-runner portion so as to extend from one of the first surface and the second surface to the other one;
a second gate portion linked with a second device forming portion of the device forming portions;
a second sub-runner portion formed in the first surface of the frame portion so as to link the second gate portion with the main-runner portion;
and a second sub-through-hole formed in the second sub-runner portion so as to extend from one of the first surface and the second surface to the other one;
wherein in plan view, the first sub-through-hole has, along a second direction along which the first sub-runner portion extends, a first portion located on the side of the main-runner portion and a second portion located on the side of the gate portion relative to the first portion,
wherein in plan view, the second sub-through-hole has, along the second direction along which the second sub-runner portion extends, a third portion located on the side of the main-runner portion and a fourth portion located on the side of the gate portion relative to the third portion,
wherein in plan view, a maximum opening width of the first and second sub-through-holes in the second direction is greater than a maximum opening width of the first and second sub-through-holes in a third direction perpendicular to the second direction, and
wherein in plan view, an opening width of the first and the second sub-through-holes in the third direction gradually decreases from the first or third portion to an end portion of the second or fourth portion on the side of the first or second gate portion,
(b) after the step (a), arranging a plurality of semiconductor chips over the device forming portions, respectively;
(c) after the step (b), supplying a resin into a first cavity of the molding die covering a first semiconductor chip in the first device forming portion through a main runner of a molding die covering the main-runner portion, a first subsidiary runner of the molding die covering the first sub-runner portion, and the first gate portion of the leadframe, and supplying a resin into a second cavity of the molding die covering a second semiconductor chip in the second device forming portion through the main runner, a second subsidiary runner of the molding die covering the second sub-runner portion, and the second gate portion of the leadframe, and thereby forming a plurality of device sealing portions that seal the semiconductor chips at the device forming portions, a main-runner sealing portion in the main-runner portion, a first sub-runner sealing portion in the first sub-runner portion, and a second sub-runner sealing portion in the second sub-runner portion;
and
(d) after the step (c), inserting a pin into each of the main-through-hole, the first sub-through-hole, and the second sub-through-hole from the second surface side of the leadframe and thereby separating the main-runner sealing portion, the first sub-runner sealing portion, and the second sub-runner sealing portion from the leadframe.

18 more elements

Dependencies are inferred from the claim text.