Back to results
US 2014/0348707 A1Published application
Ion sensitive device and method of fabrication
AssigneeElemental Sensor LLC
InventorsOliver KING SMITH, Eric Kerstan HOOBLER
Life of this patent
Estimating the term…
Abstract
A sol-gel deposition technique that forms ion sensitive layers is compatible with CMOS fabrication methods and is applied to build sensors of concentrations of solutions of selected target ions. The ion sensitive sensor may be formed on an exposed portion of a signal trace of a printed circuit board. Additionally, the ion sensitive layer may be formed within an ion sensitive field effect transistor.
Claims22
A CMOS ISFET comprising:
- a field effect transistor structure formed within a semiconductor substrate, the field effect transistor structure having a gate electrically coupled with an exposed top layer contact;
- and
- an ion sensitive material layer deposited upon the top layer contact in a sol-gel process, whereby the ion sensitive material layer is adapted to modulate the influence of the gate upon the electrical performance of the ISFET in accordance with exposure to a concentration of a target ion and the barrier material substantively isolates the ion sensitive material layer from contamination introduced from the top layer contact.
An ion sensitive circuit comprising:
- a first ion-sensitive field-effect transistor having a first gate comprising a first metal-oxide surface exposed to an ambient environment;
- a second ion-sensitive field-effect transistor having a second gate comprising a second metal-oxide surface exposed to the ambient environment, the substantively similar to the first metal-oxide surface and additionally formed by molecular imprinting;
- and
- means to measure a performance difference between the measured states of the first ion-sensitive field-effect transistor and the second ion-sensitive field-effect transistor.
1 more element
A method of fabricating a CMOS ISFET comprising:
- a. forming a field effect transistor structure within a semiconductor substrate, the field effect transistor structure having a top metal electrically coupled with a gate, and the top metal substantively exposed at a top surface of the semiconductor substrate;
- b. generally forming a passivation layer over the top surface of the semiconductor substrate;
- c. removing a portion of the passivation layer proximate to the top metal, whereby the top metal of field effect transistor structure is substantively exposed;
- d. depositing a solution comprising an ion sensitive metal oxide upon the barrier material;
- and
- e. drying the solution to form a solid layer of the ion sensitive metal oxide.
3 more elements
Dependencies are inferred from the claim text.