US 2014/0320188 A1Published application

Scannable fast dynamic register

AssigneeVIA Technologies, Inc.

InventorImran Qureshi

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Abstract

A scannable fast dynamic register including a data and scan enable circuit, a precharge circuit, a select circuit, a store circuit, and a scan input enable circuit. The data and scan enable circuit pulls a first precharge node to a discharge node in response to the clock upon evaluation in normal mode. The precharge circuit precharges first and second precharge nodes high, in which one of the precharged nodes discharges depending upon whether a data block evaluates. The store circuit and an output gate are responsive to the second precharge node to provide the output. The select circuit is interposed before the store circuit to allow injection of scan data in a scan mode. In scan mode, the scan input enable circuit provides scan data to the select and store circuits. The scan input enable circuit also includes a store circuit which operates with the first store circuit in a master-slave configuration.

Claims19

Dependent claims

A scannable fast dynamic register, comprising:

a data and scan enable circuit coupled between a first precharge node and a discharge node and receiving at least one data input and a scan enable input, wherein said data and scan enable circuit pulls said first precharge node to said discharge node when a clock node transitions from a first clock state to a second clock state and either when said data block evaluates or when said scan enable input is asserted, but otherwise does not pull said first precharge node to said discharge node;
a precharge circuit that precharges both a second precharge node and said first precharge node high while said clock node is in said first clock state, that releases said first precharge node and pulls said discharge node low when said clock node transitions to said second clock state, and that discharges said second precharge node low when said first precharge node remains high after said clock node transitions to said second clock state;
a select circuit having a first input coupled to said second precharge node, having a second input coupled to a scan data node, and having a selected output;
a store circuit having a store input receiving said selected output and having an output coupled to a store node, wherein said store circuit passes a state of said selected output to said store node while said clock node is in said second clock state, and wherein said store circuit holds a last state of said store node when said clock node is in said first clock state;
a scan input enable circuit that passes a state of a scan input to said scan data node when said scan enable input is asserted and when said clock node is in said first clock state, that forces said scan data node high when said scan enable signal is de-asserted and when said clock node is in said first clock state, and that holds a last state of said scan data node when said clock node is at said second clock state;
and
an output logic gate that drives an output node to a state based on states of said second precharge node and said store node.

4 more elements

An integrated circuit, comprising:

a clock node and a scan enable node, wherein said scan enable node receives a scan enable signal indicative of a scan mode;
and
at least one scannable fast dynamic register, each comprising:
a data and scan enable circuit coupled between a first precharge node and a discharge node and receiving at least one data input and having a scan enable input receiving said scan enable signal, wherein said data and scan enable circuit pulls said first precharge node to said discharge node when said clock node transitions from a first clock state to a second clock state either when said data block evaluates or when said scan enable signal is asserted, but otherwise does not pull said first precharge node to said discharge node;
a precharge circuit that precharges both a second precharge node and said first precharge node high while said clock node is in said first clock state, that releases said first precharge node and pulls said discharge node low when said clock node transitions to said second clock state, and that discharges said second precharge node low only if said first precharge node remains high after said clock node transitions to said second clock state;
a select circuit having a first input coupled to said second precharge node, having a second input coupled to a scan data node, and having a selected output;
a store circuit having a store input receiving said selected output and having an output coupled to a store node, wherein said store circuit passes a state of said selected output to said store node while said clock node is in said second clock state, and wherein said store circuit holds a last state of said store node when said clock node is in said first clock state;
a scan input enable circuit that passes a state of a scan input to said scan data node when said scan enable input is asserted and when said clock node is in said first clock state, that forces said scan data node high when said scan enable signal is de-asserted and when said clock node is in said first clock state, and that holds a last state of said scan data node when said clock node is at said second clock state;
and
an output logic gate that drives an output node to a state based on states of said second precharge node and said store node.

7 more elements

Dependencies are inferred from the claim text.