Fast dynamic register with transparent latch

An integrated circuit, comprising:

• combinatorial logic which provides at least one data input;
• a clock node;
• and
• a fast dynamic register, comprising:
• a data block coupled between a first precharge node and a discharge node, wherein said data block receives said at least one data input and evaluates by pulling said first precharge node to said discharge node when said clock node transitions from a first clock state to a second clock state;
• a precharge circuit that precharges both a second precharge node and said first precharge node high while said clock node is in said first clock state, that releases said first precharge node and pulls said discharge node low when said clock node transitions to said second clock state, and that discharges said second precharge node low when said first precharge node remains high after said clock node transitions to said second clock state;
• a transparent latch having a latch input coupled to said second precharge node and an output coupled a store node, wherein said transparent latch is transparent to pass a state of said second precharge node to said store node while said clock node is in said second clock state, and wherein said transparent latch latches said store node when said clock node is in said first clock state;
• and
• an output logic gate that drives an output node to a state based on states of said second precharge node and said store node.

A method of registering data, comprising:

• precharging a first precharge node high while a clock signal is at a first clock state;
• evaluating at least one data input and maintaining the first precharge node high after the clock signal transitions to a second clock state when the at least one data input does not evaluate, and discharging the first precharge node low when the at least one data input evaluates when the clock signal transitions to the second clock state;
• precharging a second precharge node high while the clock signal is in the first clock state;
• discharging the second precharge node low if the first precharge node remains high after the clock signal transitions to the second logic state, and otherwise maintaining the second precharge node high;
• latching a state of a store node when the clock signal is at the first clock state, and passing a state of the second precharge node to the store node when the clock signal is at the second clock state;
• and
• asserting an output node to a state based on the second precharge node and the store node.