Method of manufacturing semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorShinji MORI
Life of this patent
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Abstract
According to one embodiment, a method includes forming a first SiGe layer having a first profile of a concentration of Ge on a semiconductor substrate, forming a second SiGe layer having a second profile of a concentration of Ge on the first SiGe layer, the second profile lower than a first peak of the first profile, forming a mask layer on the second SiGe layer, etching the first and second SiGe layers by anisotropic etching using the mask layer as a mask to form trenches, selectively removing the first SiGe layer exposed into the trenches to form a cavity under the second SiGe layer, and oxidizing side and lower surfaces of the second SiGe layer exposed in the trenches and the cavity to increase the concentration of Ge in the second SiGe layer.
Claims16
A method of manufacturing a semiconductor device, the method comprising:
- forming a first SiGe layer having a first profile of a concentration of Ge on a semiconductor substrate;
- forming a second SiGe layer having a second profile of a concentration of Ge on the first SiGe layer, the second profile lower than a first peak of the first profile;
- forming a mask layer on the second SiGe layer;
- etching the first SiGe layer and the second SiGe layer by anisotropic etching using the mask layer as a mask to form trenches;
- selectively removing the first SiGe layer exposed into the trenches to form a cavity under the second SiGe layer;
- and
- oxidizing side and lower surfaces of the second SiGe layer exposed in the trenches and the cavity to increase the concentration of Ge in the second SiGe layer.
The method of claim. 6, further comprising:
- forming a second insulating layer on the semiconductor substrate,
- forming a Si layer or the second insulating layer, and
- forming a CMOS circuit by forming a p-channel FET on the second SiGe layer and by forming an n-channel FET on the Si layer.
Dependencies are inferred from the claim text.