Efficient Hardware Structure For Sorting/Adding Multiple Inputs Assigned To Different Bins

A method for performing bin addition, the method comprising:

• a first adder circuit receiving a first input signal and a second input signal, each input signal comprising (i) a numeric data value and (ii) an address associated with the input signal;
• evaluating the addresses associated with the first input signal and the second input signal;
• and
• producing a first output signal comprising (i) a sum of the numeric data values of the first and second input signals and (ii) an address corresponding to one of the addresses associated with the first input signal and the second input signal, if the addresses of the first and second input signals satisfy a predetermined criteria.

A hardware-implemented bin adder for evaluating addresses of a plurality of bin-adder input signals and accumulating the data values of only those bin-adder input signals having addresses that meet a predetermined criteria, the hardware-implemented bin adder comprising:

• an array of cascaded adder circuits connected in a round-robin configuration, wherein each cascaded adder circuit is adapted to:
• receive two input signals, each input signal comprising (i) a numeric data value and (ii) an address associated with the input signal;
• evaluate the addresses associated with the two input signals;
• produce a first output signal comprising (i) a sum of the numeric data values of the two input signals and (ii) an address corresponding to one of the addresses associated with the two input signals, if the addresses of two input signals satisfy a predetermined criteria.