US 2014/0278213 A1 · Overlay Sampling Methodology

Abstract

One embodiment relates to a method to achieve enhanced overlay control while maintaining manufacturing throughput for a fabrication process. Locations of a plurality of alignment structures on a wafer comprising a plurality of reticle fields are determined with a layout tool to define a layout-based wafer map. The topography of the wafer is then measured as a function of wafer position by a surface measuring tool. The layout-based wafer map is then projected onto the measured wafer topography to define a modeled wafer map. A subset of alignment structure locations are measured with an alignment tool in an in-line fabrication flow so as not to delay subsequent fabrication steps. Disagreement between the measured alignment structure locations and modeled alignment structure locations is then minimized mathematically to enhance overlay control while maintaining manufacturing throughput.

Claims20

Dependent claims

A method of wafer alignment, comprising:

defining a layout-based wafer map by determining designed locations of a plurality of alignment structures with a layout tool;
obtaining a measured surface topography of a wafer surface as a function of wafer position with a surface measuring tool;
defining a modeled wafer map comprising modeled alignment structure locations by projecting the layout-based wafer map onto the measured surface topography;
defining a measured wafer map comprising measured alignment structure locations by measuring a subset of alignment structure locations on the wafer with an alignment tool;
and
adjusting the measured wafer map and the modeled wafer map to minimize disagreement between the measured alignment structure locations and the modeled alignment structure locations.

3 more elements

A method of wafer alignment, comprising:

measuring a surface topography of a wafer to a first resolution with an optical tool or a physical tool;
defining a modeled wafer map by projecting a layout-based wafer map onto a measured surface topography, wherein the layout-based wafer map comprises designed locations of a plurality of alignment structures as defined in a layout tool;
defining a measured wafer map by measuring a subset of alignment structure locations to a second resolution with an alignment tool, wherein the second resolution is less than the first resolution;
and
combining the measured wafer map and the modeled wafer map to define a full wafer map.

2 more elements

A metrology system, comprising:

a light source configured to provide electromagnetic radiation to a wafer comprising a plurality of alignment structures, wherein the electromagnetic radiation is filtered by a patterning apparatus;
an alignment stage configured to retain the wafer and further configured to measure locations of the plurality of alignment structure to define a measured wafer map;
and
a computational unit configured to minimize disagreement between modeled alignment structure locations and measured alignment structure locations.

1 more element

Dependencies are inferred from the claim text.

Overlay Sampling Methodology

Life of this patent

Overlay Sampling Methodology

Life of this patent

Abstract

Claims20