Method and apparatus for low latency communication in an automatic testing system

A method of processing event information in a plurality of successive cycles, the method comprising:

• during a first cycle, generating a message at each of a plurality of first circuits;
• buffering each message for a variable length of time in one of a first plurality of buffers, each of the first plurality of buffers associated with one of the plurality of first circuits;
• during a second cycle, setting a value at a first position of the communication path coupled to a first buffer of the first plurality of buffers, wherein the first plurality of buffers are coupled to the communication path in a first order;
• in each of a plurality of cycles following the second cycle, communicating the value along the communication path to a subsequent position along the communication path, the subsequent position associated with a subsequent buffer in the first order and updating the value by aggregating the value with a message from the buffer at the subsequent position, thereby generating an aggregated indication;
• and
• during a third cycle, providing the aggregated indication to each of one or more second circuits.

An interface circuit for an automatic test system in which a communication path carries messages, comprising:

• a plurality of input ports;
• a plurality of output ports;
• a reference clock input;
• a first plurality of buffers coupled to the reference clock input, each buffer of the first plurality of buffers coupled to an input port and configured to receive messages at a time controlled by the reference clock;
• a communication path configured to receive the plurality of messages from the first plurality of buffers and to perform aggregation of the messages, thereby generating an aggregated indication;
• and
• a second plurality of buffers, each buffer of the second plurality of buffers coupled to an output port, configured to store an aggregated indication and to synchronously output the aggregated indication to a respective output port.