Overflow detection and correction in state machine engines
AssigneeMicron Technology, Inc.
InventorBrian Lewis Brown
Life of this patent
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Abstract
State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.
Claims37
A state machine engine, comprising:
- a state machine lattice comprising a plurality of configurable elements;
- a storage location configured to store data to be transmitted to the state machine lattice;
- and
- an inter-rank (IR) bus control system configured to receive an indication of an amount of data locations being utilized in the storage location of the state machine engine and transmit a halt signal configured to halt a write operation of the state machine engine based, at least in part, on the amount of data locations being utilized in the storage location.
A device, comprising:
- a first state machine engine, comprising:
- a first state machine lattice comprising a plurality of configurable elements;
- a first storage location configured to store data to be transmitted to the first state machine lattice;
- and
- a first inter-rank (IR) bus control system configured to receive a first indication of an amount of data locations being utilized in the first storage location of the first state machine engine and transmit a first halt signal configured to halt a write operation of the first state machine engine based, at least in part, on the first indication of the amount of data locations being utilized in the first storage location;
- a second state machine engine, comprising:
- a second state machine lattice comprising a plurality of configurable elements;
- a second storage location configured to store data to be transmitted to the second state machine lattice;
- and
- a second IR bus control system configured to receive a second indication of an amount of data locations being utilized in the second storage location of the second state machine engine and transmit a second halt signal configured to halt a write operation of the second state machine engine based, at least in part, on the second indication of the amount of data locations being utilized in the second storage location;
- and
- a communication bus coupled to the first state machine engine and the second state machine engine.
A state machine engine, comprising an inter-rank (IR) bus control system configured to halt a write operation of data to a state machine lattice, wherein the state machine lattice comprises a plurality of configurable elements and each of the plurality of configurable elements comprises a plurality of memory cells configured to analyze the data and to output a result of the analysis.
A method, comprising:
- storing data in a storage location to be transmitted to a state machine lattice;
- receiving at an inter-rank (IR) bus control system an indication of an amount of data locations being utilized in the storage location;
- and
- transmitting from the IR bus control system a halt signal configured to halt a write operation based, at least in part, on the indication of the amount of data locations being utilized in the storage location.
Dependencies are inferred from the claim text.