Local and global reduction of critical dimension (cd) asymmetry in etch processing
AssigneeApplied Materials, Inc.
InventorsKang-lie Chiang, Olivier Luere, Jinhan Choi
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Abstract
Local and global reduction of critical dimension (CD) asymmetry in etch processing is described. In an example, a method of etching a wafer of to form a plurality of staircase structures with reduced local and global asymmetry involves forming a photoresist layer on a plurality of micron-scale semiconductor structures. The photoresist layer is then trimmed with a high pressure and pulsed plasma etch process performed in a reverse MESA mode.
Claims20
A method of etching a wafer of to form a plurality of staircase structures with reduced local and global asymmetry, the method comprising:
- forming a photoresist layer on a plurality of micron-scale semiconductor structures;
- and
- trimming the photoresist layer with a high pressure plasma etch process, a pulsed plasma etch process, or a pulsed, high pressure plasma etch process.
A method of etching a wafer of to form a plurality of staircase structures with reduced local and global asymmetry, the method comprising:
- forming a photoresist layer on a plurality of micron-scale semiconductor structures;
- and
- trimming the photoresist layer with a plasma etch process performed in a reverse MESA mode.
A non-transitory machine-accessible storage medium having instructions stored thereon which cause a data processing system to perform a method of etching a wafer of to form a plurality of staircase structures with reduced local and global asymmetry, the method comprising:
- forming a photoresist layer on a plurality of micron-scale semiconductor structures;
- and
- trimming the photoresist layer with a high pressure plasma etch process, a pulsed plasma etch process, or a pulsed, high pressure plasma etch process.
A non-transitory machine-accessible storage medium having instructions stored thereon which cause a data processing system to perform a method of etching a wafer of to form a plurality of staircase structures with reduced local and global asymmetry, the method comprising:
- forming a photoresist layer on a plurality of micron-scale semiconductor structures;
- and
- trimming the photoresist layer with a plasma etch process performed in a reverse MESA mode.
Dependencies are inferred from the claim text.