Method for Integrated Circuit Patterning

A method of forming a target pattern, the method comprising:

• forming a mandrel pattern on a substrate, the mandrel pattern having a first line and a second line spaced from each other in a first direction wherein the first line has a first dimension in the first direction and a second dimension in the second direction and the second line has a third dimension in the first direction and a fourth dimension in the second direction;
• reducing the first dimension and the third dimension;
• forming a first spacer around the first line and a second spacer around the second line thereby defining a gap between the first spacer and the second spacer;
• forming a cut pattern on the substrate between the first spacer and the second spacer wherein the cut pattern partially overlaps the first spacer and the second spacer;
• removing the first line and the second line, thereby leaving a first opening within the first spacer and a second opening within the second spacer;
• and
• shrinking the first spacer and the second spacer in the first direction, thereby enlarging the gap between the first spacer and the second spacer and enlarging both the first opening and the second opening.

A method of forming a target pattern, the method comprising:

• forming a mandrel pattern on a substrate, the mandrel pattern having a plurality of lines;
• forming spacers around the plurality of lines;
• forming a cut pattern partially overlapping the spacers;
• etching the mandrel pattern using the cut pattern as an etch mask, thereby defining a plurality of openings with sidewalls of the spacers, the cut pattern, and a portion of the mandrel pattern underneath the cut pattern;
• and
• shrinking the spacers and the cut pattern thereby to enlarge the plurality of openings.