Double patterning method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Ying Lee, Jyu-Horng Shieh
Life of this patent
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Abstract
Self-aligned double patterning methods that can be used in back-end-of-line (BEOL) processing and other stages of integrate circuit device manufacturing. In these methods, line termini are masked prior to self-aligned double patterning. The self-aligned double patterning involves forming a mandrel, the shape of which is determined by a lithographic mask. That same lithographic mask is used prior to self-aligned double patterning to trim the mask that determines the locations of line termini. The methods provide precise positioning of the line termini mask relative to the line locations determined by self-aligned double patterning. The methods forms consistent end-of-line shapes and allow line termini to be placed more closely together than would otherwise be feasible.
Claims20
A process of forming an integrated circuit device, comprising:
- forming a first mask layer over a substrate;
- forming a second mask layer over the first mask layer;
- patterning the second mask layer by a process that includes exposing a first photoresist through a first lithographic mask;
- forming a sacrificial layer over the first mask layers and the patterned second mask layer;
- patterning the sacrificial layer to form a mandrel by a processes that includes exposing a second photoresist through the first lithographic mask;
- depositing a spacer material over the mandrel;
- etching the spacer material to form spacers on the sides of the mandrel;
- removing the mandrel;
- etching through the first mask layer with the remaining second mask layer and the spacers providing a mask;
- and
- treating the substrate using the remaining first mask layer as a mask.
A method of forming an integrated circuit device, comprising:
- forming a first hard mask layer over a substrate;
- forming a second hard mask layer over the first hard mask layer;
- forming a first photoresist layer over the first and second hard mask layers;
- exposing the first photoresist through a mandrel mask;
- developing the first photoresist to form a mask;
- patterning the second hard mask layer to form a second layer mask that defines locations at which conductive lines that will be formed in the substrate will end, patterning comprising etching the second hard mask using the first photoresist as a mask and the first hard mask layer as an etch stop layer;
- performing a self-aligned double-patterning of the first hard mask layer to form a first layer mask, wherein the first layer mask defines locations at which conductive lines will be formed in the substrate, wherein the first layer remains intact where it is masked by the second layer, and wherein the mandrel mask is used to form a mandrel;
- forming trenches in the substrate by etching with first layer mask, and optionally the second layer mask as well, providing a mask;
- and
- filling the trenches with conductive metal to form the conductive lines.
A method of forming an integrated circuit device, comprising:
- forming a first hard mask layer over a substrate;
- forming a second hard mask layer over the first hard mask layer;
- patterning the second hard mask layer to form islands;
- and
- performing a self-aligned double-patterning of the first hard mask layer;
- wherein self-aligned double-patterning comprises forming a mandrel using a mandrel mask;
- and
- the second hard mask layer is trimmed using the mandrel mask;
- self-aligned double patterning forms line-shaped openings in the first hard mask;
- the islands mask termini of the line-shaped openings.
Dependencies are inferred from the claim text.