Bipolar Junction Transistors, Memory Arrays, and Methods of Forming Bipolar Junction Transistors and Memory Arrays

A method of forming a memory array, comprising:

• implanting first type dopant into a memory array region of a semiconductor material to form a first type doped region;
• forming first trenches along a first direction within the first type doped region to a first depth;
• reinforcement doping the bottoms of the first trenches with second type dopant and then filling the first trenches with one or more electrically insulative materials;
• forming second trenches along a second direction within the first type doped region to a second depth which is deeper than the first depth;
• the first and second trenches together forming an array of pedestals of the semiconductor material;
• reinforcement doping the bottoms of the second trenches with first type dopant and then filling the second trenches with one or more electrically insulative materials;
• after filling the first and second trenches with electrically insulative materials, counter-doping an upper portion of the first type doped region to form a first stack comprising a second type doped region over a first type doped region;
• counter-doping an upper portion of the first stack to form a second stack comprising a second type doped region between a pair of first type doped regions;
• the second type doped region comprising base regions of bipolar transistors, the bottom first type doped region being a collector region of the bipolar transistors and the top first type doped region comprising emitter regions of the bipolar transistors;
• forming memory cells over and electrically coupled with at least some of the emitter regions;
• wherein the first trenches extend only partially through the base regions;
• wherein the second trenches extend entirely through the base regions but only partially through the collector region;
• and
• wherein one of the first and second types is p-type and the other is n-type.

A method of forming a plurality of bipolar junction transistors, comprising:

• implanting first type dopant into a semiconductor material to form a first type doped region;
• forming first trenches along a first direction within the first type doped region to a first depth;
• filling the first trenches with one or more electrically insulative materials;
• forming second trenches along a second direction within the first type doped region to a second depth which is deeper than the first depth, the second direction intersecting the first direction;
• filling the second trenches with one or more electrically insulative materials;
• an array of pedestals of the semiconductor material being patterned by the forming of the first and second trenches;
• after forming the array of pedestals, counter-doping an upper portion of the first type doped region to form a first stack comprising a second type doped region over a first type doped region;
• counter-doping an upper portion of the first stack to form a second stack comprising a second type doped region between a pair of first type doped regions;
• one of the first type doped regions being a top region of the second stack and the other of the first type doped regions being a bottom region of the second stack;
• wherein the first trenches extend only partially through the second type doped region;
• wherein the second trenches extend entirely through the second type doped region but only partially through the bottom region of the second stack;
• wherein one of the first and second types is p-type and the other is n-type;
• wherein the semiconductor material comprises monocrystalline silicon;
• counter-doping a portion of the top region of the second stack with second type dopant to form base contact regions;
• and
• reinforcement doping along bottoms of the first trenches with second type dopant prior to filling the first trenches with the one or more electrically insulative materials.