MOSFETs with Channels on Nothing and Methods for Forming the Same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsGeorgios Vellianitis, Mark van Dal, Blandine Duriez
Life of this patent
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Abstract
A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer.
Claims20
A method comprising:
- performing an epitaxy to grow a semiconductor layer, wherein the semiconductor layer comprises a top portion over a semiconductor region, and wherein the semiconductor region is between two insulation regions that are in a substrate;
- recessing the insulation regions to expose portions of sidewalls of the semiconductor region;
- etching a portion of the semiconductor region, wherein an etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap;
- forming a gate dielectric over the semiconductor layer;
- and
- forming a gate electrode over the gate dielectric.
A method comprising:
- performing an epitaxy to grow an epitaxy semiconductor layer over a semiconductor region, wherein the semiconductor region comprises a middle portion and end portions on opposite sides of the middle portion;
- etching the semiconductor region to remove the middle portion of the semiconductor region to form a recess, wherein a center part of each of the end portions of the semiconductor region remains after the etching;
- forming a gate dielectric over the epitaxy semiconductor layer;
- and
- forming a gate electrode over the gate dielectric.
A method comprising:
- performing a first recess to recess Shallow Trench Isolation (STI) regions to have a first top surface, wherein a top portion of a semiconductor region in the STI regions is over the first top surface;
- forming an epitaxy semiconductor layer on a top surface and sidewalls of the top portion of the semiconductor region;
- performing a second recess to recess the STI regions to have a second top surface, wherein a bottom end of the epitaxy semiconductor layer is over, and is spaced apart from, the second top surface, with an intermediate portion of the semiconductor region exposed;
- etching an intermediate portion of the semiconductor region to form an air gap, wherein the air gap is between the epitaxy semiconductor layer and a remaining bottom portion of the semiconductor region;
- forming a gate dielectric over a middle portion of the epitaxy semiconductor layer, with the gate dielectric overlapping the air gap;
- and
- forming a gate electrode over the gate dielectric.
Dependencies are inferred from the claim text.