Method for fabricating a semiconductor device

A method for fabricating a semiconductor device, the method comprising:

• forming a plurality of first gate patterns including a top portion and a bottom portion on a first active region of a substrate and a plurality of second gate patterns including a top portion and a bottom portion on a second active region of the substrate;
• forming a sacrificial layer contacting the bottom portions of the first gate patterns;
• forming a first spacer on lateral surfaces of the top portions of the first gate patterns after forming the sacrificial layer;
• removing the sacrificial layer after forming the first spacer;
• and
• forming a plurality of first recesses on lateral surfaces of the first gate patterns after removing the sacrificial layer.

A method for fabricating a semiconductor device, the method comprising:

• sequentially forming an insulation layer, an electrode layer and a hard mask layer on a first active region of a substrate and on a second active region of the substrate;
• patterning the insulation layer, the electrode layer and the hard mask layer to form a plurality of first gate stacks including a first gate insulation layer, a first gate electrode and a first gate hard mask sequentially stacked on the first active region of the substrate and a plurality of second gate stacks including a second gate insulation layer, a second gate electrode and a second gate hard mask sequentially stacked on the second active region of the substrate;
• forming a spacer layer covering the first gate stacks including the first gate insulation layer, the first gate electrode and the first gate hard mask and the second gate stacks including the second gate insulation layer, the second gate electrode and the second gate hard mask;
• etching the spacer layer to form a first spacer on a sidewall of the first gate insulation layer, the first gate electrode and the first gate hard mask of the first gate stacks and a second spacer on a sidewall of the second gate insulation layer, the second gate electrode and the second gate hard mask of the second gate stacks to thereby respectively form a plurality of first gate patterns including a top portion and a bottom portion on the first active region of the substrate and a plurality of second gate patterns including a top portion and a bottom portion on the second active region of the substrate;
• forming a sacrificial layer contacting the bottom portions of the first gate patterns but not contacting top portions of the first gate patterns;
• forming a third spacer on lateral surfaces of the top portions of the first gate patterns after forming the sacrificial layer;
• removing the sacrificial layer after forming the third spacer;
• forming a plurality of first recesses on lateral surfaces of the first gate patterns after removing the sacrificial layer;
• forming a plurality of second recesses by etching the first recesses;
• and
• forming a plurality of semiconductor patterns in the second recesses, wherein a portion of the semiconductors patterns are elevated relative to a top surface of the substrate, at an interface between the first gate patterns and the substrate and wherein the semiconductor patterns contact lateral surfaces of the first spacers of the first gate patterns.