Semiconductor arrangement and formation thereof

A method of semiconductor fabrication, comprising:

• forming a plurality of first transistors having a first operating voltage, the plurality of first transistors comprising a plurality of first gate structures over a first transistor region of a substrate, a plurality of low voltage shallow wells adjacent the plurality of first gate structures and a plurality of low voltage pocket implants adjacent the plurality of first gate structures;
• and
• forming a plurality of second transistors having a second operating voltage adjacent the plurality of first transistors, the forming a plurality of second transistors comprising:
• forming a first high voltage photoresist over the plurality of first gate structures, over the first transistor region and over a plurality of second gate structures, the plurality of second gate structures over a second transistor region of the substrate, such that a plurality of high voltage implant areas of the substrate adjacent the plurality of second gate structures and a plurality of second gate top portions of the plurality of second gate structures are exposed;
• performing a high voltage LDD implant at a first high energy to implant a first high voltage dopant into the plurality of high voltage implant areas to form a plurality of high voltage shallow wells adjacent the plurality of second gate structures;
• and
• performing a high voltage pocket implant at a second high energy to implant a second high voltage dopant into the plurality of high voltage implant areas to form a plurality of high voltage pocket implants adjacent the plurality of second gate structures.