Methods for fabricating integrated circuits with semiconductor substrate protection

A method for fabricating an integrated circuit, the method comprising:

• forming a plurality of gate electrode structures overlying a semiconductor substrate;
• forming a first sacrificial oxide layer overlying the semiconductor substrate;
• patterning a first implant mask overlying the first sacrificial oxide layer and a portion of the gate electrode structures to expose a portion of the first sacrificial oxide layer adjacent the gate electrode structures after forming the first sacrificial oxide layer, wherein patterning the first implant mask results in masked gate electrode structures and unmasked gate electrode structures;
• implanting conductivity determining ions into the semiconductor substrate, through the first sacrificial oxide layer;
• removing the first implant mask after implanting the conductivity determining ions into the semiconductor substrate;
• removing the first sacrificial oxide layer after implanting the conductivity determining ions into the semiconductor substrate;
• forming a second sacrificial oxide layer overlying the semiconductor substrate after removing the first sacrificial oxide layer;
• patterning a second implant mask overlying the second sacrificial oxide layer and overlying unmasked gate electrode structures left exposed after patterning the first implant mask;
• implanting conductivity determining ions into the semiconductor substrate, through the second sacrificial oxide layer;
• and
• patterning an additional implant mask overlying one of the first sacrificial oxide layer or the second sacrificial oxide layer after removing the first implant mask or the second implant mask, wherein the additional implant mask is formed overlying unmasked gate electrode structures left exposed by the first implant mask and the second implant mask.

A method for fabricating an integrated circuit, the method comprising:

• forming a plurality of gate electrode structures overlying a semiconductor substrate, wherein the plurality of gate electrode structures comprises N-type gate electrode structures and P-type gate electrode structures;
• selectively masking a portion of the gate electrode structures with an epitaxy mask to produce masked N-type gate electrode structures and unmasked P-type gate electrode structures;
• etching trenches adjacent the unmasked P-type gate electrode structures and epitaxially growing semiconductor material within the trenches;
• removing the epitaxy mask after epitaxially growing the semiconductor material to expose the N-type gate electrode structures;
• forming a first sacrificial oxide layer overlying the semiconductor substrate after removing the epitaxy mask;
• patterning a first implant mask overlying the first sacrificial oxide layer and the N-type gate electrode structures to expose a portion of the first sacrificial oxide layer adjacent the P-type gate electrode structures after forming the first sacrificial oxide layer, wherein patterning the first implant mask produces masked N-type gate electrode structures and unmasked P-type gate electrode structures;
• implanting P-type conductivity determining ions into the semiconductor substrate, through the first sacrificial oxide layer;
• removing the first implant mask after implanting the P-type conductivity determining ions into the semiconductor substrate;
• removing the first sacrificial oxide layer after implanting the P-type conductivity determining ions into the semiconductor substrate;
• forming a second sacrificial oxide layer overlying the semiconductor substrate after removing the first sacrificial oxide layer;
• patterning a second implant mask overlying the second sacrificial oxide layer and overlying unmasked P-type gate electrode structures left exposed after patterning the first implant mask;
• implanting N-type conductivity determining ions into the semiconductor substrate, through the second sacrificial oxide layer.