Vertical Doping and Capacitive Balancing for Power Semiconductor Devices

A method for making a power semiconductor device, comprising:

• providing a semiconductor substrate;
• providing an epitaxial layer on the substrate, the epitaxial layer comprising:
• a bottom portion containing a first conductivity type dopant in a substantially constant, first concentration throughout the bottom portion;
• and
• an upper portion containing a first conductivity type dopant having a second concentration lower than the first concentration;
• providing a trench in the epitaxial layer;
• forming a transistor structure in the trench;
• and
• forming a well region in the upper part of the epitaxial layer adjacent the trench, the well region containing a second conductivity type dopant that is opposite the first conductivity type.

A method for making a shielded gate MOSFET device, comprising:

• providing a semiconductor substrate;
• providing an epitaxial layer on the substrate, the epitaxial layer comprising:
• a bottom portion containing a first conductivity type dopant in a substantially constant, first concentration throughout the bottom portion;
• and
• an upper portion containing a first conductivity type dopant having a second concentration lower than the first concentration;
• providing a trench in the epitaxial layer;
• forming an insulating layer on the bottom and sidewalls of the trench;
• forming a conductive shield on the insulating layer;
• forming an interlevel dielectric layer on the conductive shield;
• forming a gate on the interlevel dielectric layer;
• forming an insulation cap on the gate;
• and
• forming a well region in the upper part of the epitaxial layer adjacent the trench, the well region containing a second conductivity type dopant that is opposite the first conductivity type.