Integrated circuits and methods for fabricating integrated circuits with gate electrode structure protection

A method for fabricating an integrated circuit comprising:

• forming a P-type gate electrode structure and an N-type gate electrode structure overlying a semiconductor substrate, wherein the gate electrode structures each comprise a gate electrode overlying a gate dielectric layer and a nitride cap overlying the gate electrode;
• etching trenches into the semiconductor substrate adjacent the P-type gate electrode structure;
• epitaxially growing a semiconductor material within the trenches;
• implanting conductivity determining ions into the semiconductor substrate using the P-type gate electrode structure as a mask to form a source region and a drain region for the P-type gate electrode structure;
• removing the nitride cap from the P-type gate electrode structure after epitaxially growing the semiconductor material within the trenches and prior to implanting the conductivity determining ions into the semiconductor substrate to form the source region and the drain region for the P-type gate electrode structure;
• implanting conductivity determining ions into the semiconductor substrate using the N-type gate electrode structure as a mask to form a source region and a drain region for the N-type gate electrode structure;
• removing the nitride cap from the N-type gate electrode structure after implanting the conductivity determining ions into the semiconductor substrate to form the source region and the drain region for the N-type gate electrode structure.

An integrated circuit comprising:

• a P-type gate electrode structure and an N-type gate electrode structure overlying a semiconductor substrate, wherein the gate electrode structures each comprise a gate electrode overlying a gate dielectric layer;
• first sidewall spacers comprising a nitride disposed adjacent to the P-type gate electrode structure and the N-type gate electrode structure;
• and
• third sidewall spacers comprising a nitride only disposed adjacent to the P-type gate electrode structure;
• wherein the first sidewall spacers adjacent to the N-type gate electrode structure are thinner than the first sidewall spacers adjacent to the P-type gate electrode structure.