Vertical Power MOSFET And IGBT Fabrication Process With Two Fewer Photomasks

A process for making a power semiconductor device comprising:

• on an n-conductivity type semiconductor substrate forming a layer of gate oxide;
• introducing n-conductivity type dopant into the substrate through the gate oxide;
• depositing a layer of polycrystalline silicon on the gate oxide;
• masking the layer of polycrystalline silicon to define first locations for p-conductivity type impurity;
• implanting p-conductivity type impurity to provide p-well regions;
• introducing additional p-conductivity type impurity and n-conductivity type impurity through the layer of polycrystalline silicon;
• providing a masking layer over an upper surface of the layer of polycrystalline silicon and over exposed sidewalls of the layer of polycrystalline silicon to thereby define second locations within the first locations;
• and
• performing a shallow etch of the semiconductor substrate through the second locations.

A method of manufacturing a power semiconductor device comprising:

• (a) forming a layer of gate oxide on an n-conductivity type semiconductor substrate;
• (b) implanting an n-conductivity type dopant into the substrate through the gate oxide;
• (c) depositing a layer of polycrystalline silicon onto the gate oxide;
• (d) depositing a first layer of photoresist onto the layer of polycrystalline silicon thereby defining a plurality of exposed regions;
• (e) etching the layer of polycrystalline silicon at each of the plurality of exposed regions;
• (f) forming a p-well region by implanting a p-conductivity type dopant into the plurality of exposed regions;
• (g) implanting a p-conductivity type dopant through the plurality of exposed regions into the p-well region;
• (h) implanting a n-conductivity type dopant through the plurality of exposed regions into the p-well region;
• and
• (i) depositing a second layer of photoresist onto the layer of polycrystalline silicon and portions of the substrate, wherein the layer of polycrystalline silicon has an upper surface and a plurality of sidewalls, and wherein the second layer of photoresist overlies both the upper surface and the sidewalls, and wherein portions of the substrate are exposed between the sidewalls.

A method of manufacturing a power semiconductor device comprising:

• (a) forming a p-well region in an n-conductivity type semiconductor substrate;
• (b) forming a strongly doped p-conductivity type layer within the p-well region, wherein the strongly doped p-conductivity type layer is formed after the forming of the p-well region in (a) without applying a mask between the forming of the p-well region in (a) and the forming of the strongly doped p-conductivity type layer in (b);
• and
• (c) forming a strongly doped n-conductivity type layer within the p-well region, wherein the strongly doped n-conductivity type layer contacts the strongly doped p-conductivity type layer of (b) such that the n-conductivity type layer is disposed entirely above the strongly doped p-conductivity type layer of (b), wherein the strongly doped n-conductivity type layer is formed without applying a mask between the forming of the strongly doped p-conductivity type layer in (b) and the forming of the strongly doped n-conductivity type layer in (c), and wherein the power semiconductor device is manufactured using no more than four masks.