Fabrication of 3d chip stacks without carrier plates
AssigneeApplied Materials, Inc.
InventorsSesh RAMASWAMI, Chin Hock TOH, Niranjan KUMAR
Life of this patent
Estimating the term…
Abstract
A method of fabricating a 3D chip stack uses an interposer and an electronic circuit substrate comprising a plurality of electronic circuits. The electrical contacts of the electronic circuit substrate are bonded and electrically coupled to bumps of the interposer. A molding compound is applied over the electronic circuits to form a molded structure. The molded structure is thinned to have a second molded thickness that is less than the first molded thickness, and the interposer is thinned to a second interposer thickness that is less than a first interposer thickness.
Claims15
A method of fabricating a 3D chip stack, the method comprising:
- (a) providing an interposer having a first interposer thickness and a front surface comprising bumps;
- (b) providing an electronic circuit substrate comprising a plurality of electronic circuits and a connector surface having electrical contacts;
- (c) bonding and electrically coupling the electrical contacts of the connector surface of the electronic circuit substrate to the bumps of the interposer;
- (d) applying a molding compound over the electronic circuits to form a molded structure having a first molded thickness;
- (e) thinning the molded structure to have a second molded thickness that is less than the first molded thickness;
- and
- (f) thinning the interposer to form a thinned interposer having a second interposer thickness that is less than the first interposer thickness.
A method of fabricating a 3D chip stack, the method comprising:
- (a) providing an interposer having a first interposer thickness, a front surface comprising bumps, a plurality of through-silicon vias, and a back surface;
- (b) providing an electronic circuit substrate comprising a plurality of electronic circuits and a connector surface having electrical contacts;
- (c) bonding and electrically coupling the electrical contacts of the connector surface of the electronic circuit substrate to the bumps of the interposer;
- (d) applying a molding compound over the electronic circuits to form a molded structure having a first molded thickness;
- (e) thinning the molded structure to a second molded thickness that is less than the first molded thickness and to expose top surfaces of the electronic circuits;
- and
- (f) thinning the interposer from its back surface to form a thinned interposer having a second interposer thickness that is less than the first interposer thickness and to expose contact regions of the through-silicon vias.
A method of fabricating a 3D chip stack, the method comprising:
- (a) providing an interposer having a first interposer thickness and a front surface comprising bumps;
- (b) providing an electronic circuit substrate comprising a plurality of electronic circuits and a connector surface having electrical contacts;
- (c) bonding and electrically coupling the electrical contacts of the connector surface of the electronic circuit substrate to the bumps of the interposer;
- (d) applying a molding compound over the electronic circuits to form a molded structure having a first molded thickness;
- (e) thinning the molded structure to a second molded thickness that is less than the first molded thickness and to expose top surfaces of the electronic circuits;
- (f) thinning the interposer to from a thinned interposer having a second interposer thickness that is less than the first interposer thickness;
- and
- (g) forming a plurality of through-silicon vias in the thinned interposer by etching holes through a back surface of the thinned interposer and depositing an oxide liner and metal into the etched holes.
Dependencies are inferred from the claim text.