Method and system for forming a diagonal pattern using charged particle beam lithography
AssigneeD2S, Inc.
InventorsEtienne Jacques, Jin Choi, Kazuyuki Hagiwara
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AssigneeD2S, Inc.
InventorsEtienne Jacques, Jin Choi, Kazuyuki Hagiwara
Estimating the term…
A method and system for fracturing or mask data preparation is disclosed in which the central core portion of a diagonal pattern is fractured using overlapping variable shaped beam (VSB) shots, and an outer portion of the diagonal pattern is fractured using non-overlapping VSB shots. A transition region is interposed between the central core and outer pattern portions, and transition region shots are generated so as to produce in the transferred pattern a smooth transition in pattern characteristics such as line edge roughness or period of waviness, from the central core portion of the pattern to the outer portion of the pattern. Methods for forming a semiconductor device layout pattern on a reticle or substrate are also disclosed.
A method for fracturing or mask data preparation of a semiconductor device layout design to be formed on a wafer, the layout design comprising a diagonal pattern, wherein a portion of the diagonal pattern comprises a constant-width or nearly constant-width track on the wafer, and wherein an inner transition region of the diagonal pattern is adjoined on one side by an outer transition region and on the other side by a central core region, the method comprising the steps of:
A method for forming a semiconductor device layout pattern on a reticle, the layout pattern to be formed on a wafer using a lithographic process with the reticle, the layout pattern comprising a diagonal pattern, wherein a portion of the diagonal pattern comprises a constant-width or nearly constant-width track on the wafer, and wherein an inner transition region of the diagonal pattern is adjoined on one side by an outer transition region and on the other side by a central core region, the method comprising the steps of:
A method for forming a semiconductor device layout pattern on a substrate, the layout pattern comprising a diagonal pattern, wherein a portion of the diagonal pattern comprises a constant-width or nearly constant-width track on the wafer, the method comprising the steps of:
A method for fracturing or mask data preparation of a semiconductor device layout design comprising a diagonal pattern, the method comprising the steps of:
A system for fracturing or mask data preparation of a semiconductor device layout design to be formed on a wafer using a lithographic process with a reticle, the layout design comprising a diagonal pattern, wherein a portion of the diagonal pattern comprises a constant-width or nearly constant-width track on the wafer, and wherein an inner transition region of the diagonal pattern is adjoined on one side by an outer transition region and on the other side by a central core region, the system comprising:
Dependencies are inferred from the claim text.