Circuit arrangements
AssigneeIntel Deutschland GmbH
InventorMatthias Eberlein
Life of this patent
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Abstract
A circuit arrangement may include: a first bipolar transistor; a second bipolar transistor; wherein the circuit arrangement is configured to provide a first current flowing through the first bipolar transistor and a second current flowing through the second bipolar transistor; a resistor connected between a first input of the first bipolar transistor and a first input of the second bipolar transistor; a first circuit configured to provide a first current flowing through the resistor to a first input node of the first bipolar transistor, and a second circuit configured to provide a reference current to the first input node of the first bipolar transistor, wherein the first current and the reference current have different temperature dependencies.
Claims22
A circuit arrangement, comprising:
- a first bipolar transistor;
- a second bipolar transistor;
- wherein the circuit arrangement is configured to provide a first current flowing through the first bipolar transistor and a second current flowing through the second bipolar transistor;
- a resistor electrically coupled between a first input of the first bipolar transistor and a first input of the second bipolar transistor;
- a first circuit configured to provide a first current flowing through the resistor to a first input node of the first bipolar transistor,
- a second circuit configured to provide a reference current to the first input node of the first bipolar transistor, wherein the first current and the reference current comprise different temperature dependencies.
A temperature sensing circuit arrangement, comprising:
- a first current source configured to provide a first current depending on the temperature of the circuit arrangement;
- a second current source configured to provide a second current depending on the temperature of the circuit arrangement and on a current control signal;
- a summing node electrically coupled to the first current source and the second current source, wherein the summing node is configured to receive the first current and the second current;
- a current comparator electrically coupled to the summing node and configured to provide an output signal depending on a difference between the first current and the second current;
- a control circuit configured to receive the output signal of the current comparator and to provide the current control signal for controlling the second current source;
- wherein temperature dependency of the first current source is different from temperature dependency of the second current source.
A circuit arrangement, comprising:
- an amplifier;
- and
- a buffer coupled to an output of the amplifier, the buffer formed by an n-channel metal oxide semiconductor field effect transistor and a p-channel metal oxide semiconductor field effect transistor;
- wherein the gate terminal of the n-channel metal oxide semiconductor field effect transistor and the gate terminal of the p-channel metal oxide semiconductor field effect transistor are coupled to the output of the amplifier;
- wherein a drain terminal of the n-channel metal oxide semiconductor field effect transistor is coupled to a first reference potential and a drain terminal of the p-channel metal oxide semiconductor field effect transistor is coupled to a second reference potential different from the first reference potential;
- wherein a source terminal of the n-channel metal oxide semiconductor field effect transistor is coupled to a source terminal of the p-channel metal oxide semiconductor field effect transistor to form a control output of the circuit arrangement.
A method for providing a temperature indication, the method comprising:
- setting a first current;
- setting a second current, the first current and the second current comprising different temperature dependencies;
- sensing the difference between the first current and the second current and providing a temperature indication.
Dependencies are inferred from the claim text.