Bit error pattern analyzer and method
AssigneeViavi Solutions Deutschland GmbH
InventorsReiner SCHNIZLER, Paul Brooks
Life of this patent
Estimating the term…
Abstract
The invention relates to a method and device for testing a data link. A single-lane or multi-lane bit error tester that transmits one or more PRBS signals through the data link is augmented with a raw bit error buffer for storing bit error information for each detected error event and an error pattern analyzer. Most frequently occurring intra-lane bit error patterns, inter-lane word error patterns, and bit slip patterns are identified and their characteristics are analyzed so as to provide information indicative of root causes of the detected bit errors and bit slips.
Claims17
A method of testing a data link having an input port and an output port, the method comprising:
- a) providing a first pseudo-random bit sequence (PRBS) to the input port of the data link;
- b) using a first PRBS analyzer connected to the output port of the data link to detect bit error events in a first received bit sequence, wherein the first received bit sequence corresponds to the first PRBS transmitted over the data link;
- c) for each bit error event detected by the first PRBS analyzer in at least a portion of the first received bit sequence, writing bit error information into an error buffer, wherein the bit error information comprises PRBS analyzer state information corresponding to the detected bit error event;
- d) using an error pattern analyzer to read the bit error information from the error buffer, to associate detected errors with specific bit patterns, and to generate therefrom error pattern analysis information that is indicative of a cause of the detected bit errors;
- and,
- e) providing the error pattern analysis information to a user.
A bit error pattern tester for testing digital signal transmission through a data link, comprising:
- a PRBS generator for feeding a PRBS signals into an input port of the data link;
- a PRBS analyzers for detecting bit errors in a received bit sequence, wherein the received bit sequence corresponds to the PRBS signal received from an output port of the data link after transmission over the data link;
- an error data buffer;
- an error data generator operatively connected to the PRBS analyzer for receiving therefrom bit error information for each detected bit error event, and for writing the bit error information into the error buffer;
- an error pattern analyzer that is operatively connected to the error data buffer and is configured to associate detected errors with specific bit patterns based on the bit error information saved in the error data buffer, and to generate bit error pattern analysis information that is indicative of a cause of the detected bit errors;
- and,
- an output device for providing the bit error pattern analysis information to the user.
Dependencies are inferred from the claim text.