Amplifier circuit with improved slew rate

An amplifier circuit for improved slew rate comprises

• a common mode rejection stage;
• a primary gain stage;
• an output stage;
• said primary gain stage comprising a circuit for enhancing a first output impedance;
• a reduced compensation capacitor being needed to obtain a frequency pole, wherein said frequency pole is the same to an ordinary amplifier's frequency pole;
• said compensation capacitor being added to only one side of a differential op-amp circuit;
• and
• an output voltage being taken from the same side where said phase compensation capacitor is added.

An amplifier circuit for improved slew rate comprises

• a common mode rejection stage;
• a primary gain stage;
• an output stage;
• said primary gain stage comprising a circuit for enhancing a first output impedance;
• a reduced compensation capacitor being needed to obtain a frequency pole, wherein said frequency pole is the same to an ordinary amplifier's frequency pole;
• said compensation capacitor being added to only one side of a differential op-amp circuit;
• an output voltage being taken from the same side where said phase compensation capacitor is added;
• said primary gain stage adopting a cascade configuration;
• said cascade configuration preventing a systematic offset;
• said cascade configuration regulating a common mode input rage of said amplifier circuit;
• said common mode rejection stage being before said primary gain stage;
• said common mode rejection stage rejecting a common mode signal;
• said differential op-amp circuit comprising resistors r1, r2, r3, r4 and R;
• said cascade configuration comprising transistors M16, M17, M22 and M23;
• said primary gain stage comprising a common source circuit;
• said common mode rejection stage comprising transistors M8, M9, M10, M11, M18 and M19;
• and
• the resistors r1, r2 and R being larger than the resistors r3 and r4.