US 2014/0237441 A1 · Method and Apparatus for Placing and Routing Partial Reconfiguration Modules

Abstract

A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.

Claims20

Dependent claims

A method for designing a system on a target device, comprising:

routing static logic modules and partial reconfigurable (PR) modules on the target device;
arbitrating routing resources that are in conflict from the routing to static logic modules and PR modules competing for the routing resources;
assigning unused routing resources from the routing to static logic modules and PR modules having conflicts;
and
re-routing the static logic modules and PR modules having conflicts with the routing resources arbitrated and assigned.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

14/152,624Filed 10 Jan 2014

Priority

3 Mar 2011

Published

21 Aug 2014

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 30/3953
Routing: detailed
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 30/347
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: physical level, e.g. placement or routing
G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement

Abstract

Facts

Application

14/152,624Filed 10 Jan 2014

Priority

3 Mar 2011

Published

21 Aug 2014

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 30/3953
Routing: detailed
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
G06F 30/347
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: physical level, e.g. placement or routing
G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement

Method and Apparatus for Placing and Routing Partial Reconfiguration Modules

Life of this patent

Abstract

Claims20

Method and Apparatus for Placing and Routing Partial Reconfiguration Modules

Life of this patent

Abstract

Claims20