Look-up based fast logic synthesis
AssigneeSynopsys, Inc.
InventorsYiu-Chung Mang, Sanjay Dhar, Vishal Khandelwal, Kok Kiong Lee
Life of this patent
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Abstract
Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells.
Claims6
A method for performing circuit synthesis, the method comprising:
- receiving a cell in a circuit design that is to be optimized;
- performing, by a computer, a table lookup operation on one or more tables based on information associated with the cell to obtain a set of optimal cell configurations, wherein the one or more tables enable the set of optimal cell configurations to be looked up based on the information associated with the cell;
- and
- replacing the cell in the circuit design with a cell configuration selected from the set of optimal cell configurations.
A method for creating a lookup table for use during circuit synthesis, the method comprising:
- receiving a maximum input capacitance value, a library arc group, and an output load;
- for each equivalent cell configuration whose input capacitance is less than or equal to the maximum input capacitance value, determining, by a computer, a cost metric for a library arc corresponding to the library arc group based on the output load;
- identifying one or more cell configurations that have optimal or near optimal cost metrics;
- and
- associating the maximum input capacitance value and the output load with the one or more cell configurations in a table for the library arc group, wherein the table enables the one or more optimal cell configurations to be looked up based on the maximum input capacitance value and the output load.
A method for performing circuit synthesis, the method comprising:
- receiving a cell for optimization;
- determining, by a computer, timing criticality of the cell;
- determining timing criticality of a driver cell that drives an input of the cell;
- in response to determining that the cell is timing critical, optimizing the cell for timing, but not for area or power leakage;
- in response to determining that the cell is not timing critical, but the driver cell is timing critical, optimizing the cell for timing and area, but not for power leakage;
- and
- in response to determining that both the cell and the driver cell are not timing critical, optimizing the cell for area and power leakage, but not for timing.
Dependencies are inferred from the claim text.