Method and apparatus for reading data from non-volatile memory

An apparatus comprising:

• an array of flash memory cells arranged in rows and columns, wherein each of the flash memory cells comprises a floating gate transistor having a floating gate configured to store charge indicative of a data digit, and wherein a column of the array comprises a string of floating gate transistors arranged in series from source to drain;
• a sense circuit configured to detect a value associated with the charge indicative of the data digit stored in the floating gate of a selected flash memory cell of the array;
• and
• a circuit configured to determine a state associated with the data digit of the selected flash memory cell based at least partly on processing the value in accordance with a Viterbi algorithm.

An apparatus comprising:

• memory cells each comprising a floating gate transistor having a floating gate configured to store charge indicative of a data digit;
• a sense circuit configured to sense an electrical condition of a selected memory cell of the memory cells;
• and
• a circuit configured to determine a logical state of the selected memory cell based at least in part on the sensed electrical condition and at least one of an electrical condition or a logical state associated with an adjacent memory cell of the memory cells, so as to compensate for one or more electrons associated with the adjacent memory cell being trapped on the floating gate of the selected memory cell.

A method of determining states of data digits stored in a memory array, the method comprising:

• detecting values associated with charges indicative of data digits stored by selected memory cells of the memory array, wherein each of the selected memory cells comprises a floating gate transistor configured to store charge indicative of a data digit;
• processing the detected values in accordance with a Viterbi algorithm;
• and
• determining states of the data digits stored by the floating gate transistors of the selected memory cells based at least partly on the processed detected values;
• wherein the method is performed by electronic circuits.