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US 2014/0237322 A1Published application
Storage at m bits/cell density in n bits/cell analog memory cell devices, m>n
AssigneeApple Inc.
InventorsOfir Shalvi, Naftali Sommer, Uri Perlmutter, Dotan Sokolov
Life of this patent
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Abstract
A method for data storage includes accepting data for storage in a memory that includes multiple analog memory cells and supports a set of built-in programming commands. Each of the programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells. The subset of the memory cells is programmed to store M pages of the data, M>N, by performing a sequence of the programming commands drawn only from the set.
Claims20
An apparatus, comprising:
- a processing unit configured to receive a first command from a host to read data from a memory, wherein the memory includes a plurality of planes;
- and
- an interface coupled to the memory, wherein the interface is configured to:
- send a second command to the memory to read data from a first plane of the plurality of planes responsive to the processing unit receiving the first command;
- and
- receive data from the first plane of the plurality of planes;
- wherein the processing unit is further configured to decode an Error Correction Code (ECC) of the data read from the first plane of the plurality of planes;
- wherein the interface is further configured to send, in parallel to the processing unit decoding the ECC of the data read from the first plane, a third command to the memory to read data from a second plane of the plurality of planes.
5 more elements
A method, comprising:
- receiving a command from a host to read data from a memory, wherein the memory includes a plurality of planes;
- reading data from a first plane of the plurality of planes;
- decoding an Error Correction Code (ECC) of data read from the first plane of the plurality of planes responsive to a determination that the reading of the first plane of the plurality of planes has completed;
- and
- reading, in parallel with decoding the ECC of the data read from the first plane, data from a second plane of the plurality of planes.
2 more elements
A system, comprising:
- a host;
- and
- a memory device coupled to the host, wherein the memory device includes a plurality of planes, and wherein the memory device is configured to:
- receive a command from the host;
- read data from a first plane of the plurality of planes;
- decode an Error Correction Code of the data read from the first plane of the plurality of planes responsive to a determination that the reading of the data from the first plane of the plurality of planes has completed;
- and
- read data, in parallel with the decoding of the ECC of the data read from the first plane of the plurality of planes, from a second plane of the plurality of planes.
5 more elements
Dependencies are inferred from the claim text.