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US 2014/0237318 A1Published application
Bandwidth optimization in a non-volatile memory system
AssigneeSanDisk Enterprise IP LLC
InventorsJames Fitzpatrick, Amirhossein Rafati
Life of this patent
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Abstract
A method of bandwidth optimization in a non-volatile memory system includes: retrieving hard data bits; generating soft information from the hard data bits; applying a lossless compression to the soft information for calculating syndrome bits; and executing a low density parity check (LDPC) iterative decode on the hard data bits and the syndrome bits.
Claims20
A method of bandwidth optimization in a non-volatile memory system comprising:
- retrieving hard data bits;
- generating soft information from the hard data bits;
- applying a lossless compression to the soft information for calculating syndrome bits;
- and
- executing a low density parity check (LDPC) iterative decode on the hard data bits and the syndrome bits.
2 more elements
A non-volatile memory system comprising:
- a non-volatile memory cell having hard data bits;
- a destination register, coupled to a non-volatile memory cell, for retrieving the hard data bits;
- a soft information module, coupled to the destination register, for calculating a soft information from the hard data bits;
- a lossless compression module, coupled to the soft information module, configured to calculate syndrome bits from the soft information;
- and
- an error correction module, coupled to the lossless compression module, for generating host data by executing a low density parity check (LDPC) iterative decode on the hard data bits and the syndrome bits.
3 more elements
A non-volatile memory system comprising:
- a non-volatile memory device includes:
- a non-volatile memory cell having hard data bits,
- a destination register, coupled to the non-volatile memory cell, for retrieving the hard data bits,
- a soft information module, coupled to the destination register, for capturing a reliability of the hard data bits, and
- a lossless compression module, coupled to the soft information module, for calculating syndrome bits;
- and
- a controller module, coupled to the non-volatile memory device, includes:
- an error correction module for generating a host data by executing a low density parity check (LDPC) iterative decode on the hard data bits and the syndrome bits.
5 more elements
Dependencies are inferred from the claim text.