Scan Warmup Scheme for Mitigating DI/DT During Scan Test

An integrated circuit device, comprising:

• a first set of logic elements;
• a shift logic configured to load a stimulus to the first set of logic elements at a scan clock first frequency equal to a test clock frequency, unload a scan test response from the first set of logic elements at the scan clock first frequency, and capture a scan test response by a shift logic at a scan clock second frequency;
• and
• a scan warmup unit configured to adjust the scan clock from the first frequency to the second frequency, wherein the scan clock second frequency is equal to a system clock frequency and mitigate a drop in voltage of a power supply to the integrated circuit associated with a transition of the scan clock from the first frequency to the second frequency, by reducing a change in current draw within a predetermined time period.

A non-transitory computer-readable medium storing instructions that, when executed by a computer system in a manufacturing facility, adapts the manufacturing facility to create an apparatus, the apparatus comprising:

• a first set of logic elements;
• a shift logic configured to load a stimulus to the first set of logic elements at a scan clock first frequency equal to a test clock frequency, unload a scan test response from the first set of logic elements at the scan clock first frequency, and capture a scan test response by a shift logic at a scan clock second frequency;
• and
• a scan warmup unit configured to adjust the scan clock from the first frequency to the second frequency, wherein the scan clock second frequency is equal to a system clock frequency and mitigate a drop in voltage of a power supply to the integrated circuit associated with a transition of the scan clock from the first frequency to the second frequency, by reducing a change in current draw within a predetermined time period.