Interconnections for plural and hierarchical p1500 test wrappers

A test architecture within an integrated circuit comprising:

• A. a plurality of core wrappers each having a serial input, a serial output, and control inputs, the control inputs including a clock input, a shift input, a capture input, an update input, a reset input, an enable input, and a core select input;
• B. input circuitry having a serial input, a plurality of serial outputs, each selectively coupled to the serial input, and control inputs, each serial output being connected to the serial input of a core wrapper;
• C. output circuitry having a plurality of serial inputs, a serial output, and a control input, each serial input being connected to the serial output of a core wrapper and each serial input being selectively coupled to the serial output;
• and
• D. a link instruction register having a serial input, a serial output, control inputs, and control outputs,
• i. the control inputs including a clock input coupled to the clock input of the core wrappers, a shift input coupled to the shift input of the core wrappers, a capture input coupled to the capture input of the core wrappers, an update input coupled to the update input of the core wrappers, and a link select input coupled to the select input of the core wrappers,
• ii. the control outputs including plural enable outputs, each enable output being coupled to the enable input of a core wrapper, and the control outputs including select outputs coupled to the control inputs of the input circuitry and the output circuitry,
• iii. the serial input and the serial output of the link instruction register being connected in series with the serial input of the input circuitry and the serial output of the output circuitry, and
• iv. the link instruction register including an instruction register connected to the serial input and to the control outputs, and a multiplexer connected to the serial input, the serial output, and the select input.