Test control using existing ic chip pins
AssigneeFairchild Semiconductor Corporation
InventorJuha-Matti Kujala
Life of this patent
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Abstract
An apparatus and method are provided for testing normal circuitry in an integrated circuit, the method including writing test protocols into a plurality of test registers using an enable pin and a switch pin in a first mode, storing a logic high signal in one of the plurality of test registers once the writing is completed, switching from the first mode to a second mode if the one of the plurality of test registers stores the logic high signal, and testing the normal circuitry using the enable pin and the switch pin in the second mode.
Claims20
An integrated circuit comprising:
- functional circuitry to be tested;
- data interface circuitry;
- an analog and digital test signal multiplexer array;
- a plurality of test registers;
- a first multiplexer configured to output to a switch pin and to select an input from the data interface circuitry in a first mode and from the analog and digital test signal multiplexer array in a second mode;
- a second multiplexer configured to receive an input from the switch pin and to output to the data interface circuitry in the first mode and to the analog and digital test signal multiplexer array in the second mode;
- a third multiplexer configured to receive an input from an enable pin and to output to the data interface circuitry in the first mode and to the analog and digital test signal multiplexer array in the second mode;
- latch circuitry coupled to the first multiplexer, the second multiplexer and the third multiplexer and configured to select the first mode or the second mode based on an input from the enable pin and an input from one of the plurality of test registers.
A method for testing normal circuitry in an integrated circuit, the method comprising:
- writing test protocols into a plurality of test registers using an enable pin and a switch pin in a first mode;
- storing a logic high signal in one of the plurality of test registers once the writing is completed;
- switching from the first mode to a second mode if the one of the plurality of test registers stores the logic high signal;
- and
- testing the normal circuitry using the enable pin and the switch pin in the second mode.
An integrated circuit comprising:
- one or more operational pins configured to input/output data to functional circuitry during conventional functionality of the integrated circuit;
- latch circuitry configured to select a first mode or a second mode for the integrated circuit based on an input from an enable pin of the one or more operational pins and an input from one of a plurality of test registers;
- and
- one or more multiplexers coupled to the one or more operational pins and configured to couple the one or more operational pins to data interface circuitry in the first mode and an analog and digital test signal multiplexer array in the second mode.
Dependencies are inferred from the claim text.