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US 2014/0237307 A1Published application
Generic address scrambler for memory circuit test engine
AssigneeIntel Corporation
InventorsDarshan Kobla, David Zimmerman, Vimal Natarajan
Life of this patent
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Abstract
A generic address scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory stack having one or more of coupled memory elements, a built-in self-test circuit including a generic programmable address scrambler for the mapping of logical addresses to physical addresses for the memory elements, and one or more registers to hold pro-gramming values for the generic programmable address scrambler.
Claims23
A memory device comprising:
- a memory stack including one or more of coupled memory elements;
- a built-in self-test circuit, the built-in self-test circuit including a generic programmable address scrambler for the mapping of logical addresses to physical addresses for the memory elements;
- and
- one or more registers to hold programming values for the generic programmable address scrambler.
1 more element
A logic element for a memory device comprising:
- a memory controller for a memory stack of the memory device;
- a built-in self-test circuit, the built-in self-test circuit including a generic programmable address scrambler for the mapping for logical addresses to physical addresses for the memory stack;
- and
- a configuration register to hold programming values for the generic programmable address scrambler.
1 more element
A system including;
- a bus to connect elements of the system;
- a processor coupled with the bus to process data for the system;
- a transmitter to transmit data, a receiver to receive data, or both;
- an omnidirectional antenna for data transmission, data reception or both;
- and
- memory coupled to the bus to hold data for processing by the processor, the memory including a stacked memory device, the stack memory device including:
- a memory stack including one or more of coupled memory elements,
- a built-in self-test circuit, the built-in self-test circuit including a generic programmable address scrambler for the mapping for logical addresses to physical addresses for the memory elements, and
- one or more registers to hold programming values for the generic programmable address scrambler.
6 more elements
Dependencies are inferred from the claim text.