US 2014/0237302 A1 · CHARACTERIZATION AND FUNCTIONAL TEST IN A PROCESSOR OR SYSTEM UTILIZING CRITICAL PATH MONITOR TO DYNAMICALLY MANAGE OPERATIONAL TIMING MARGIN

Abstract

Guardband validation for a device having a critical path monitor involves first applying multiple calibration settings to the monitor during functional operation of the processor, and recording corresponding guardbands which result in reduced timing margin. A desired guardband can later be selected for validation. The calibration settings can be based on delays for a critical path. A calibration test procedure can be used to determine the calibration delays for different operating frequencies or voltages that are set or, alternatively, the calibration delays can be set and resultant frequencies measured which are used to calculate the guardband amounts. The critical path monitor may include a modified calibration delay circuit which provides a calibrated delay signal to a critical path synthesis circuit, and the multiple calibration settings can be applied by changing delay taps of the calibration delay circuit in response to a bias delay signal from a power management controller.

Claims24

Dependent claims

A method of guardband validation for an electronic device having a monitor which controls one or more operational parameters of the electronic device based on current operating conditions, comprising:

functionally operating the electronic device while the monitor is active;
applying multiple calibration settings to the monitor during said operating;
for each calibration setting, recording a corresponding guardband amount;
selecting one of the guardband amounts for validation;
and
carrying out guardband testing of the electronic device while the monitor is active using the calibration setting that corresponds to the selected guardband amount.

3 more elements

A computer system comprising:

one or more processors which process program instructions, at least one of said processors having at least one critical path monitor which controls a functional clock frequency of the at least one processor based on current operating conditions, the at least one critical path monitor having at least one production calibration setting which results in a normal operational timing margin for the at least one processor;
a memory hierarchy connected to said one or more processors;
and
power management control logic which applies at least one bias calibration setting to said critical path monitor for guardband testing, resulting in a reduced timing margin for the processor that is less than the normal operational timing margin.

1 more element

Dependencies are inferred from the claim text.

Characterization and functional test in a processor or system utilizing critical path monitor to dynamically manage operational timing margin

Life of this patent

Characterization and functional test in a processor or system utilizing critical path monitor to dynamically manage operational timing margin

Life of this patent

Abstract

Claims24