Masking power usage of co-processors on field-programmable gate arrays
AssigneeEmpire Technology Development LLC
InventorsKevin Fine, Ezekiel Kruglick
Life of this patent
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Abstract
Technologies are generally described for masking power usage of co-processors on field-programmable gate arrays. In some examples, one or more moat brick circuits may be implemented around a co-processor loaded on a held-programmable gate array (FPGA). The moat brick circuits may be configured to use negative feedback and/or noise to mask the power usage variations of the co-processor from other co-processors on the FPGA.
Claims32
A method for masking co-processor power usage on a field-programmable gate array (FPGA), the method comprising:
- determining a power usage of a co-processor to be loaded on the FPGA, wherein the co-processor is a hardware accelerator for a virtual machine;
- generating at least one moat brick circuit based on the determined power usage;
- loading the co-processor on the FPGA;
- loading the at least one moat brick circuit on the FPGA such that the at least one moat brick circuit is physically adjacent to the co-processor and at least partially masks the power usage of the co-processor;
- and
- forming a composite co-processor including the co-processor and the at least one moat brick circuit.
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A configuration controller to mask co-processor power usage on a field-programmable gate array (FPGA), the controller comprising:
- a moat builder module configured to:
- determine a power usage of a co-processor to be loaded on the FPGA, wherein the co-processor is a hardware accelerator for a virtual machine;
- and
- generate at least one moat brick circuit based on the determined power usage;
- and
- a processing module configured to:
- load the co-processor on the FPGA;
- load the at least one moat brick circuit on the FPGA such that the at least one moat brick circuit is physically adjacent to the co-processor and at least partially masks the power usage of the co-processor;
- form a composite co-processor including the co-processor and the at least one moat brick circuit;
- and
- load the composite co-processor on the FPGA according to a placer algorithm.
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A cloud-based datacenter configured to mask co-processor power usage, the datacenter comprising:
- a field-programmable gate array (FPGA);
- and
- a configuration controller configured to:
- determine a power usage of a co-processor to be loaded on the FPGA, wherein the co-processor is a hardware accelerator for a virtual machine;
- generate at least one moat brick circuit based on the determined power usage;
- load the co-processor on the FPGA;
- load the at least one moat brick circuit on the FPGA such that the at least one moat brick circuit is physically adjacent to the co-processor and at least partially masks the power usage of the co-processor;
- form a composite co-processor including the co-processor and the at least one moat brick circuit;
- and
- load the composite co-processor on the FPGA according to a placer algorithm.
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Dependencies are inferred from the claim text.