Data processing system

Apparatus for processing data comprising:

• first means for processing configured to operate in a first power domain;
• second means for processing configured to operate in a second power domain different from said first power domain;
• means for shared processing configured to operate in a shared power domain such that said means for first processing and said means for shared processing are configurable to operate together to form a first means for hybrid processing having access to an external memory and said second means for processing and said means for shared processing are configurable to operate together to form a second means for hybrid processing having access to said external memory, wherein said first means for hybrid processing and said second means for hybrid processing together comprise a uni-processing environment for executing a single instruction stream;
• means for execution flow transfer for transferring execution of said single instruction stream between said first means for hybrid processing and said second means for hybrid processing at a transfer execution point, wherein said execution flow transfer comprises transfer of at least one bit of processing-state restoration information from a source one of said first means for hybrid processing and said second means for hybrid processing to a destination one of said first means for hybrid processing and said second means for hybrid processing, said processing-state restoration information being information enabling said destination means for hybrid processing to successfully resume execution of said single instruction stream from said transfer execution point.

A data processing method comprising the steps of:

• operating first processing circuitry in a first power domain;
• operating second processing circuitry in a second power domain different from said first power domain;
• operating shared processing circuitry in a shared power domain and forming a first hybrid processing unit by operating said first processing circuitry and said shared processing circuitry together, said first hybrid processing unit having access to an external memory;
• forming a second hybrid processing unit by operating and said second processing circuitry and said shared processing circuitry together, said second hybrid processing unit having access to said external memory;
• providing a uni-processing environment for executing a single instruction stream, said uni-processing environment comprising said hybrid processing circuitry and said second hybrid processing circuitry together;
• transferring execution of said single instruction stream between said first hybrid processing circuitry and said second hybrid processing circuitry at a transfer execution point using transfer execution circuitry, wherein said execution flow transfer comprises transfer of at least one bit of processing-state restoration information from a source one of said first hybrid processing unit and said second hybrid processing unit to a destination one of said first hybrid processing unit and said second hybrid processing unit, said processing-state restoration information being information enabling said destination hybrid processing unit to successfully resume execution of said single instruction stream from said transfer execution point.