Multiple Critical Paths Having Different Threshold Voltages in a Single Processor Core
AssigneeQUALCOMM Incorporated
InventorsJoseph Victor Zanotelli, Martin Saint-Laurent
Life of this patent
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Abstract
A processor having a multi-Vt critical path is provided that includes both low-Vt devices and high-Vt devices. If the processor is operating in a high performance mode, the multi-Vt critical path is controlled so as to use the low-Vt devices. Conversely, if the processor is operating in a low power mode, the multi-Vt critical path is controlled so as to use the high-Vt devices. In this fashion, the complication of multiple processing cores is avoided in that a single processor core can operate in both the high performance mode and in the low power mode.
Claims20
A multi-mode critical path for a central processing unit (CPU), comprising:
- a high performance critical path including first logic gates coupled between an initial storage cell and a final storage cell, wherein the first logic gates are configured to be operational during a high performance mode for the CPU and to be non-operational during a low power mode for the CPU, the first logic gates comprising devices configured to have at least one of a first channel length and a first threshold voltage;
- and
- a low power critical path including second logic gates coupled between the initial storage cell and the final storage cell, wherein the second logic gates are configured to receive power during the low power mode and to not receive power during the high performance mode, the second logic gates comprising devices configured to have at least one of a second channel length and a second threshold voltage, wherein the second channel length is longer than the first channel length and the first threshold voltage is lower than the second voltage, and wherein the CPU is configured to operate using the low power critical path in the low power mode and to operate using the high performance critical path in the high performance mode.
A multi-Vt critical path for a central processing unit (CPU), comprising:
- a plurality of dual-mode logic gates coupled in a path from an initial storage gate and a final storage gate, wherein each dual-mode logic gate includes a high performance low-Vt logic gate and a corresponding low power high-Vt logic gate, and wherein each dual-mode logic gate is configured to isolate the low power high-Vt logic gate from the path during a high performance mode for the CPU and to isolate the high performance low-Vt logic gate from the path during a low power mode for the CPU.
A central processing unit (CPU), comprising:
- a high-Vt portion configured to be clocked responsive to a low speed clock during a low power mode for the CPU and to be clocked responsive to a high speed clock during a high performance mode for the CPU;
- and
- a multi-Vt critical path coupled between an initial storage cell and a final storage cell, the multi-Vt critical path including low-Vt devices configured to be selected curing the high performance mode such that the multi-Vt critical path functions as a low-Vt critical path during the high performance mode, the multi-VT critical path further including high-Vt devices configured to be selected during the low power mode such that the multi-Vt critical path functions as a high-Vt critical path during the low performance mode.
A central processing unit (CPU), comprising:
- a high-Vt portion configured to be clocked responsive to a low speed clock during a low power mode for the CPU and to be clocked responsive to a high speed clock during a high performance mode for the CPU;
- a critical path;
- and
- means for controlling the critical path to operate using low-Vt devices during the high performance mode and to operate using high-Vt devices during the low power mode.
A method, comprising:
- operating a central processing unit (CPU) in a low power mode, wherein the CPU is clocked according to a low speed clock, the CPU including a multi-Vt critical path;
- during the low power mode operation of the CPU, controlling the multi-Vt critical path to use high-Vt devices;
- operating the CPU in a high performance mode, wherein the CPU is clocked according to a high speed clock;
- and
- during the high performance mode, controlling the multi-Vt critical path to use low-Vt devices.
Dependencies are inferred from the claim text.