Simd integer multiply-accumulate instruction for multi-precision arithmetic

An apparatus comprising:

• decoding logic to receive and decode a multiply-and-accumulate (MAC) instruction for unsigned integer operations, the MAC instruction to indicate a first vector register as a first operand, a second vector register as a second operand, and a third vector register as a destination, the first vector register to store a first factor and the second vector register to store a partial sum of the MAC instruction;
• execution logic coupled to the decoding logic to multiply the first factor with an implicit second factor to generate a product, and to add the partial sum to the product to generate a result, wherein the first factor, the implicit second factor and the partial sum have a same data width and the product has twice the data width;
• and
• a set of vector registers coupled to the execution logic, wherein the set of vector registers include the third vector register to store a most significant half of the result, and the second vector register to store a least significant half of the result.

A system comprising:

• an interconnect;
• a processor coupled to the interconnect, the processor including:
• decoding logic to receive and decode a multiply-and-accumulate (MAC) instruction for unsigned integer operations, the MAC instruction to indicate a first vector register as a first operand, a second vector register as a second operand, and a third vector register as a destination, the first vector register to store a first factor and the second vector register to store a partial sum of the MAC instruction;
• execution logic coupled to the decoding logic to multiply the first factor with an implicit second factor to generate a product, and to add the partial sum to the product to generate a result, wherein the first factor, the implicit second factor and the partial sum have a same data width and the product has twice the data width;
• and
• a set of vector registers coupled to the execution logic, wherein the set of vector registers include the third vector register to store a most significant half of the result, and the second vector register to store a least significant half of the result;
• and
• a dynamic random access memory (DRAM) coupled to the interconnect.