Microprocessor

Abstract

A microprocessor according to an aspect of the present invention includes an arithmetic operation unit. The arithmetic operation unit includes: a plurality of arithmetic operation devices arranged in a multi-stage arrangement; a delay device provided to each stage of the arithmetic operation devices excluding a final stage, and configured to delay an arithmetic operation result of the arithmetic operation devices for one cycle; and a selector provided to each stage of the arithmetic operation devices excluding the final stage, and configured to select either the arithmetic operation result of the arithmetic operation devices or the arithmetic operation result delayed for one cycle in the delay device and output the selected result to the arithmetic operation device in a next stage. The microprocessor is configured to collectively process a plurality of arithmetic operations from the arithmetic operation unit by controlling a selecting condition in the selector.

Dependencies are inferred from the claim text.