Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response

A method of operating a pipeline in a parallel array processor having a first processing element (PE) and a second PE, the method comprising:

• initiating execution of a first instruction in a first PE in parallel with initiating execution of a second instruction in a second PE, wherein the first instruction is a one cycle execution instruction and the second instruction is a two cycle execution instruction;
• receiving a notification of an interrupt in the first PE and in parallel in the second PE before completing the execution of the first instruction in the first PE and before completing the execution of the second instruction in the second PE;
• completing the execution of the first instruction in the first PE and saving a first execution result in a target register specified by the first instruction;
• completing the execution of the second instruction in the second PE and saving a second execution result in an interrupt forwarding register in response to the notification without saving the second execution result in a target register specified by the second instruction;
• and
• restoring the second execution result from the interrupt forwarding register to the target register specified by the second instruction in the second PE on a return from interrupt.

A very long instruction word (VLIW) processing element (PE) comprising:

• a PE control unit initiating execution of a VLIW received in the PE, wherein the VLIW contains a first instruction that takes a single cycle to execute and a second instruction that takes two cycles to execute;
• a PE pipeline configurable in response to a notification of an interrupt, the notification received while the PE is executing the first instruction in parallel with the second instruction;
• a register file having individual registers specified by instructions in a program;
• a single cycle execution unit which executes the first instruction and upon completing execution of the first instruction, saves a first execution result to a target register located in the register file and specified by the first instruction;
• an interrupt forwarding register for storing execution results after the notification is received;
• a two cycle execution unit which executes the second instruction and upon completing execution of the second instruction, saves a second execution result in the interrupt forwarding register in response to the notification without saving the second execution result in a target register located in the register file and specified by the second instruction;
• and
• a restoring function which restores the second execution result from the interrupt forwarding register to the target register specified by the second instruction on a return from interrupt.