Apparatus and method of a concurrent data transfer of multiple regions of interest (roi) in an simd processor system

A data transfer apparatus comprising:

• a processing element array that comprises multiple processing elements controlled in a Single Instruction Multiple Data style;
• memory elements that are provided inside each of the processing elements, data access to all the memory elements of the processing elements being done in parallel;
• a control processor controlling the processing element array in the Single Instruction Multiple Data style;
• a bus system connecting all of the processing elements with each other and with the control processor;
• and
• a single memory that exchanges data with the memory elements of the processing element array, the single memory acting as data source for a read transfer and as a data sink for a write transfer,
• wherein the control processor comprises;
• a register set unit having a number of registers, each of which is temporary storage of Region Of Interest (ROI) transfer parameter set for each processing element, the transfer parameter set including at least a ROI start address inside the single memory, the width of ROI and the height of ROI;
• and
• a request address calculator that firstly shifts a position of data to be transferred horizontally and vertically inside the each ROI by adding 1 and secondly calculates the address of the position inside the single memory, using the ROI start address and a common distance that is the width of a memory region of the single memory, in addition to said vertical and horizontal position.