Apparatus and method for handling page protection faults in a computing system
AssigneeInternational Business Machines Corporation
InventorsSimon Murray, Geraint M. North
Life of this patent
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Abstract
Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.
Claims20
A computing system, comprising:
- a translator unit arranged to convert a subject code into a target code, the subject code comprising a reference to at least one subject memory page having associated subject page access attributes;
- a target processor unit arranged to execute the target code;
- a target memory associated with the target processor unit and including a page descriptor store and plurality of memory locations related to the subject memory pages, wherein address bits defining addresses of the plurality of memory locations are selected based on information in the page descriptor store according to the subject page access attributes, values of the address bits indicating a page protection condition of a corresponding subject memory page;
- and
- wherein the translator unit is arranged to allow an attempt to access a target memory location within the plurality of memory locations to proceed without an interruption in control flow, if the attempted access is within the scope of the subject page access attributes for the associated subject memory page, and wherein the translator unit is operable to detect a page protection fault based on an attempt to access a target memory location and determine a nature of the page protection fault by examining the address bits of the respective target memory location.
The computing system of claim 4, wherein the translator unit is arranged to attempt to access either the target memory location within the plurality of memory locations or to attempt to access the guard representation in accordance with the information in the page descriptor store.
A method of handling page protection faults comprising the steps of:
- converting a subject code executable that comprises a reference to at least one subject memory page having associated subject page access permissions into a target code executable by the at least one target processor and including references to a target memory, the conversion including establishing a page descriptor store according to the reference to the subject memory page and the associated subject page permissions;
- wherein the page descriptor store includes alignment checking data, the alignment checking data indicating whether an attempt to access a target memory location crosses a subject page boundary;
- and
- allowing an attempt to access the target memory location to proceed without an interruption in control flow when the attempted access is within the permissions of all the subject pages involved in the attempted access.
A non-transitory computer readable medium having instructions recorded thereon which when executed by a computing system having at least one target processor cause the computing system to perform a process comprising:
- converting a subject code executable that comprises a reference to at least one subject memory page having associated subject page access permissions into a target code executable by the at least one target processor and including references to a target memory, the conversion including establishing a page descriptor store according to the references to the subject memory pages and the associated subject page access permissions and forming a plurality of target memory locations related to the subject memory page wherein address bits defining addresses of the plurality of target memory locations are selected based on information in the page descriptor store according to the subject page access permissions, the address bits indicating a page protection condition of the subject memory page;
- and
- allowing an attempt to access a target memory location within the plurality of target memory locations to proceed without an interruption in control flow, if the attempted access is within the scope of the subject page access permissions for the subject memory page.
Dependencies are inferred from the claim text.