Efficient validation of coherency between processor cores and accelerators in computer systems

A computer system comprising:

• one or more processors which process program instructions;
• a memory device connected to said one or more processors;
• and
• program instructions residing in said memory device for testing coherency in a system design having a shared resource, at least one processor which accesses the shared resource, and at least one accelerator which accesses the shared resource, by selecting an entry of the shared resource for targeted testing during a simulation of operation of the system design, allocating a first portion of the selected entry for use by one or more first instructions from the processor, allocating a second portion of the selected entry for use by one or more second instructions from the accelerator, executing the first and second instructions using the allocated first and second portions of the selected entry subject to a coherency protocol adapted to maintain data consistency of the shared resource, and verifying correctness of data stored in the entry.

A verification tool comprising:

• a verification environment for simulating a system design having a cache memory, a plurality of processors which access the cache memory, a plurality of accelerators which access the cache memory, and a coherency mechanism adapted to maintain data consistency of the cache memory, wherein the processors and the accelerators operate during simulation at different frequencies;
• a verification control module which selects a line of the cache memory for targeted testing during a simulation of operation of the system design, allocates first portions of the selected line for use by instructions from the processors, allocates second portions of the selected line for use by instructions from the accelerators, and commands execution of the first and second instructions using the allocated first and second portions of the selected line subject to the coherency mechanism;
• and
• a correctness checker module which verifies correctness of data stored in the cache memory.