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AssigneeNVIDIA Corporation
InventorsRouslan DIMITROV, Rui BASTOS, Ziyad S. HAKURA, Eric B. LUM
Estimating the term…
A device driver calculates a tile size for a plurality of cache memories in a cache hierarchy. The device driver calculates a storage capacity of a first cache memory. The device driver calculates a first tile size based on the storage capacity of the first cache memory and one or more additional characteristics. The device driver calculates a storage capacity of a second cache memory. The device driver calculates a second tile size based on the storage capacity of the second cache memory and one or more additional characteristics, where the second tile size is different than the first tile size. The device driver transmits the second tile size to a second coalescing binning unit. One advantage of the disclosed techniques is that data locality and cache memory hit rates are improved where tile size is optimized for each cache level in the cache hierarchy.
A method for calculating a tile size for a plurality of cache memories in a cache hierarchy, the method comprising:
A non-transitory computer-readable medium including instructions that, when executed by a processing unit, cause the processing unit to calculate a tile size for a plurality of cache memories in a cache hierarchy, by performing the steps of:
A computing device comprising:
Dependencies are inferred from the claim text.