One-cacheable multi-core architecture

A first tile configured to process a request for a data block in a multi-core processor, the first tile comprising:

• a first cache;
• a first core;
• a controller configured in communication with the first cache, wherein the controller is configured to:
• receive the request for the data block, wherein the request is received from a second tile comprising a second cache and a second core,
• determine that the data block is part of a group of data blocks,
• determine that the group is stored in one cache in the multi-core processor,
• determine that the group is stored in the first cache in the first tile,
• send the data block from the first cache in the first tile to the second tile, and
• invalidate the data block sent from the first tile to the second tile and the group of data blocks in the first cache in the first tile.

A multi-core processor configured to process a request for a data block, the multi-core processor comprising:

• a first tile, wherein the first tile includes a first cache and a first controller configured in communication with the first cache;
• and
• a second tile configured in communication with the first tile,
• wherein the second tile is configured to
• generate the request for the data block, and
• send the request for the data block to the first tile,
• wherein the first tile is configured to:
• receive the request for the data block,
• determine that the data block is part of a group of data blocks,
• determine that one or more data blocks of the group are stored in the first cache in the first tile,
• send the data block from the first cache in the first tile to the second tile, and
• invalidate the data block sent from the first tile to the second tile and each data block in the one or more data blocks of the group of data blocks that are stored in the first cache in the first tile.

A multi-core processor configured to process a request for a data block, the multi-core processor comprising:

• a first tile in a die, wherein the first tile includes a first cache and a first controller configured in communication with the first cache;
• a second tile in the die and configured in communication with the first tile;
• and
• a memory configured in communication with the first tile and the second tile;
• wherein the first tile is configured to:
• generate the request for the data block;
• determine that the data block is part of a group of data blocks that is stored exclusively in one cache in the multi-core processor;
• determine that the data block is not stored in the first cache;
• determine that another data block in the group is stored in the first cache;
• in response to the determination that the data block is not stored in the first cache and the determination that the another data block in the group is stored in the first cache, send the request to the memory.

A multi-core processor configured to process a request for a first data block, the multi-core processor comprising:

• a first tile, wherein the first tile includes a first cache and a first controller configured in communication with the first cache;
• a second tile configured in communication with the first tile;
• and
• a memory configured in communication with the first tile and the second tile;
• wherein the first tile is configured to:
• generate a request to initialize a value of the first data block;
• determine that the first data block is part of a group of data blocks that is stored exclusively in one cache in the multi-core processor;
• determine that a second block in the group is stored in the first cache;
• in response to the determination that the second block in the group is stored in the first cache, store the first data block in the first cache and initialize the first data block to the value.